A logic network can be represented, for example, as a directed acyclic graph of vertices and edges, where the vertices are partitioned into primary inputs, primary outputs, and internal vertices. A Boolean function can be associated with each internal vertex in a logic network. A Boolean function, ƒ, with n inputs and m outputs can be defined as a mapping ƒ: Bn→Bm, where B can have the value 1 or 0. Input values of the logic network can be set on to the primary inputs and processed by the internal vertices. Calculated output values of the logic network can be produced at the primary outputs. Logic networks can be defined using various notations, such as, for example, using Boolean equations, hardware description languages, specifications, netlists, logic diagrams, and/or binary decisions diagrams.
The description of a logic network can be unbound (i.e., be technology-independent) or bound (i.e., be made of components that are instances of a given technology library). Typically, logic networks are first described using an unbound notation. However, for example, to actually make a digital circuit or test certain properties of a prospective digital circuit, the logic network typically needs to be bound to a given technology library. Technology mapping can transform an unbound logic network to a bound network. Various systems and methods exist to perform technology mapping and these systems and methods can be included in, for example, computer automated design (CAD) tools.
Challenges in designing and/or improving logic networks and/or circuits include, for example, reducing size, reducing area, and/or ensuring timing-robust implementations. However, in attempting to address some of these challenges, a circuit designer typically attempts to be careful to not introduce problems, such as, for example, timing hazards. Timing hazards can be caused by the timing delay of different components (e.g., logic gates, latches, multiplexers, etc.) in a circuit. When certain paths through a circuit allow a variable-change to propagate faster than other paths, a timing hazard may result. For example, if a logic gate accepts two inputs (e.g., input one and input two) and a new value for input one arrives before the corresponding new value for input two arrives, the gate output may change to reflect the arrival of input one, despite the fact that other gates leading to input two have not yet stabilized. As a result, the output of the logic gate will change before the entire sub-circuit leading to input two has stabilized. In this case, input two will not be observed by the gate, and later changes on input two may eventually cause incorrect values to appear on the gate output.
Logic networks and/or circuits can be designed to be, for example, asynchronous or synchronous. Unlike a synchronous circuit, an asynchronous circuit component is not governed by a clock circuit or global clock signal. Instead, the component waits for a signal or signals that indicate completion of instructions and operations. Circuits can be entirely asynchronous or entirely synchronous, while others can include both asynchronous and synchronous components and these components can communicate.
Avoiding and/or removing timing hazards can be a challenge in synchronous CAD flows, especially as, for example, process, temperature, and voltage variations increase in deep submicron designs. One approach to address this challenge present in synchronous designs is the use of asynchronous circuits that can accommodate timing discrepancies. Furthermore, asynchronous designs, as compared to synchronous designs, can reduce power consumption, reduce electromagnetic interference, improve robustness to parameter variations, and provide modularity of design.
One way of avoiding timing hazards in asynchronous logic networks is to ensure that the network is designed such that its output changes only after all its inputs have changed, such a network can be referred to as input-complete. An input-complete asynchronous logic network can be formed, for example, from a synchronous logic network, by replacing every logic gate in the synchronous logic network with an input-complete asynchronous block.